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Clocks are an important part of practical digital design. Suppose you have a two input AND gate. Then imagine both inputs go from zero to one, which should take the output from zero to one, also.
On paper, that seems reasonable, but in real life, the two signals might not arrive at the same time. But the errors will add up and in a more complex circuit it would be easy to get glitches while the inputs to combinatorial gates change with different delays. This makes things much simpler to design. If you need a refresher on flip flops, they are elements that remember a single bit.
A D flip flop will remember its input named D at the clock edge and hold that output until the next clock edge. There are other kinds of flip flops, like the T flip flop which toggles state or the JK flip flop which can perform several functions. This would infer a T flip flop. Usually, though, the inference is not this direct. The input might be a logic expression.
The compiler can also infer counters which are lots of flip flops:. Just as using the plus operator allowed the Verilog compiler to do the best thing for an adder, the expression above will let it build an efficient counter without you having to worry about the details. The demo circuit had three distinct parts: In English, this says that when the clock has a rising edge, check to see if the reset line is high. If it is, clear the carry latch. Otherwise, check to see if the carry is set and if so, set the carry latch.
It will remain set until a reset clears it. The Verilog tool will recognize this is a flip flop with synchronous reset. If you get really concerned about performance, you may want to investigate if your FPGA does better with an asynchronous reset and learn how your tool can be told to do that instead. But for now, this is sufficient. The realization will probably be a D type flip flop with a rising edge-sensitive clock input and a clock enable tied to the carry line.
The D input will be tied to a logic 1. This is an important Verilog feature. When you are using assignments, you always use the equal sign. If you are writing a sequential block, you almost never want to use the single equal sign, even though Verilog will allow this. That is, all the assignments in the block happen all at one time.
In simulation, that means they happen at the end statement since simulations have to pretend everything happens in parallel. In an FPGA, parallel execution is just how the hardware works. This can cause lots of timing issues and unless you are sure you need to do it and understand the ramifications, you should avoid it at all costs. You may notice that some of the variables in the Verilog code are of type wire and some are of type reg.
A wire has to be constantly driven to some value. A reg is more like a regular variable. However, you can set a value in a reg and it sticks. One problem you wind up with in Verilog is that if you make up a name, the compiler by default will assume you mean for it to be a wire unless you tell it otherwise.
This causes the compiler to throw an error if you use an undeclared net. The remainder of the Verilog takes the 12MHz clock and uses it to drive a 16 bit counter. When the counter overflows, another counter increases. When that counter reaches 91, the secondary counter goes to zero.
You can figure that out by noting that 12MHz is 83 ns or. A bit counter will overflow on the th count two to the 16 power. Do the math and that comes out to nearly 5. If you let the secondary counter go to 91, that will take almost ms. If you go to 92, you go over ms.
Note that counting to 91 or 92 only takes a 7 bit counter. A graphical representation of the situation is shown here with the code for it below. This is a form of sequential circuit and the counters will turn into a chain of flip flops when synthesized. The numbers in square brackets are telling you the number of bits in the value. So cnt1 has 16 bits numbered from 15 the most significant to 0 the least significant. Since the new design requires a clock, the testbench has to provide it.
It would be very annoying to have to write each clock transition. In English, this says: At all times, you should delay one clock cycle the 1 and then invert the clock signal and keep doing that forever.
Another item to consider is the FPGA reset:. In this case, I change the primary counter increment to hex so it will flip every other clock cycle and then changed the test for 91 down to a more reasonable value. You can see the entire code on EDAPlayground and you can even run the simulation from there. The waveform shown here will appear.
If you plan to work along, you can get a head start by installing the open source tool kit now. You can also read the next post in this series. Well if you stand upside down…. If you want to go from 12MHz to 2 Hz, why not just make a single counter that counts to 6 million? Much easier, and gives an exact result. For example, in a Spartan 6 the carry delay is about 0. So it is customary to use multiple stages of smaller counters e. When you are comparing long counters against absolute values eg counter — there is also the problem of fan-in.
The optimal design varies based on the underlying FPGA architecture, so what is optimal for one chip might be sub-optimal on another, but the general principal is the same. Or count up, and test for carry out, but initialize at value greater than 0. I am curious what the advantage is to cascading two separate counters, a bit and a 7-bit when a single counter of the appropriate width will do? For anyone who is new to FPGAs, but is familiar with programming and standard data types, the concept of using multiple, familiar-width counters may be confusing and may indicate that this is the only way to implement such a thing.
I love seeing these guides, especially these since I have only fumbled through Verilog in the past. I had originally lifted the clock code from the iCEstick demo and my original plan was to show something going on with the faster clock and maybe even talk a little about clock domains. However, I wanted to show a multiple cascaded counter just to have something a little meatier than a single flip flop and a half adder, and the double division was as good a way to do it as any.
But you make a good point. What do you think? And Al, if you do do clock domain crossing issues, can you be explicit about the difference between timing errors where different parts of the design sees different values on the same net at the same time , and metastability errors, where a flip-flop is unable to correctly sample the signal because of set-up and hold violations.
The chance of your button-push occurring in the super-tiny window that can drive a flip-flop metastable long enough cause a metastability failure is your design astronomically small — your switch would wear out before an error could be seen.
This is a big issue when people try to implement an async reset, as different parts of the design come out of reset in different clock cycles — async resets are best avoided, IMO. Continuing the series with advanced topics would be great. So for VHDL users, blocking and non-blocking statements is more or less the same as signal and variable assignment…. The BIG difference is that variables are only valid within the process statements.
Instead in VHDL you have two distinctly different types of code blocks. In the website mentioned here — http: This is completely wrong. What this code is saying is to get a register D type Flip-Flop and connect a OR b to the data input and clock the register whenever 'a' changes or 'b' changes. The synthesis engine will realise that a register is not required and remove it. VHDL allows you to write the same think using different coding styles.
The process was mainly designed for describing registers but nowadays is widely used for defining the any kind of logic specially useful when big or complex algorithms need to be described since it allows you to think sequentially. My internal parser sees it as an assignment, and I get a "assignment in a conditional expression — are you really sure you want to do that?
Capacitors and resistors are more for analog uses. Mentally, treat FPGAs as purely in the digital domain. You are commenting using your WordPress. You are commenting using your Twitter account. You are commenting using your Facebook account. Notify me of new comments via email. Notify me of new posts via email. By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies.
The compiler will recognize other types, too. The compiler can also infer counters which are lots of flip flops: